ABSTRACT
Successive Approximation analog-to-digital converters (SAR ADCs) achieve excellent power efficiency due to its simple architecture and dynamic operation, while its conversion speed is limited by its sequential conversion. Hybrid ADC takes the design advantages of multi conventional ADC architecture to optimize the conversion speed, resolution and power dissipation. This chapter introduces a hybrid ADC architecture combining the flash, SAR and pipelined ADC with interleaving and op-amp sharing schemes to achieve near GHz sampling rate and 11-bit resolution. Moreover, some digital assisted solutions are also introduced that fix the conversion errors from offset and digital-to-analog converter mismatches. The chapter covers several topics for designing the high-speed and high-resolution ADCs, including the ADC architecture, sampling front-end design for time-interleaving scheme and the digital-assisted solutions for accuracy optimization. It discusses the design challenges in ADC core as well as its peripheral interface circuits and proposes some corresponding circuit techniques to solve the problems.
