Introduction

This introduction presents an overview of the key concepts discussed in the subsequent chapters of this book. The book identifies the importance of symmetry in suppressing the up conversion of noise into close-in phase noise, and provides an explicit appreciation of cyclostationary effects and AM–PM conversion. It reviews the basics of timing and clock and data recovery circuits in high speed links, including system level considerations, limitations of the linear model, pull-in process and false lock, and a case for and key features of time domain event-driven system model to capture the effect of the circuit parameters on system performance. The chapter provides details on Integer/Frac-N, CMOS delay cell ring and LC VCO based PLL designs. It deals with Terahertz and mm-wave signal generation, synthesis and amplification with an overview on the fundamental limits. The chapter covers architecture and circuit level design techniques for the front-end circuitry of ADC-based high-speed link receivers.