ABSTRACT
This chapter reviews the basics of timing and clock and data recovery circuits in high speed links, including system level considerations, limitations of the linear model, pull-in process and false lock, and a case for and key features of time domain event-driven system model to capture the effect of the circuit parameters on system performance. It reviews the circuits for phase detection and modeling of samplers for fast and accurate system level modeling. The linear model is probably the most useful way to understand and analyze a feedback type CDR. Loop type is determined by number of integrators in the open loop transfer function. This is important because it determines the steady state behavior. The aperture of an ideal sampler is a delta function, meaning that the decision depends on the data value at only one time instant. The simplest aperture-based model sees the sampler as the series of the analog frontend described with the aperture, and an ideal slicer.
