ABSTRACT
This chapter covers circuit- and architecture-level design techniques for the front-end circuitry of ADC-based links. It focuses time-interleaved data conversion using SAR and flash topologies. The chapter looks into the opportunity of relaxing the ADC requirements using analog pre-equalization. The decision mixed-signal feedback equalizer sees additional timing and scalability challenges. On the other hand, as equalization is moved into the digital domain for ADC-based links, the ADC needs to be very fast, have reasonably high resolution and yet be very power efficient. The analog-inverter transconductor is the fundamental building block for the inverter-based FFE. The circuit architecture is identical to that of a digital inverter, but the operating point is constrained to the saturation region in the small-signal range about mid-supply. Using inverter trans-conductors in the coefficients and summing circuit results in a ratiometric FFE design where the common mode at each stage is common to the entire FFE.
