ABSTRACT
In the present era of technology, there is a requirement for devices that can consume lesser power, have high speed, and acquire smaller areas. The above requirement can be fulfilled by the devices which should be fabricated by the use of domino logic circuits. The reduction in consumed power can be obtained by reducing Vdd at the Vout node. In this paper, the footer circuit with conventional NOT gate is being replaced by T-NOT (twisted connected Transistors). The comparative analysis between them was made with various functions like consumed power, delay, and power delay product (PDP). The T-NOT gate lowers the swing of Vdd at the Vout node, which helps reduction of consumed power and enhances the speed of the circuits. The various keeper techniques were used to reduce the contention current. The switching energy (PDP) of Domino Logic Circuits can be minimised by using T-NOT Gate. The cadence virtuoso EDA tool with gdpk 45 nm technology is used to simulate all the circuits.
