ABSTRACT
As scaling down the feature size, the power dissipation becomes the major component in the domino logic circuit. In this paper, one circuit has been proposed namely, dynamic buffer with twist connect inverter (T-NOT) and sleep transistor, for reducing the power dissipation and enhancing the speed of the circuit. In the existing circuit, the conventional inverter is replaced by a twist-connected inverter. A week keeper transistor is used to provide a small amount of current at a dynamic node to prevent charge loss and improve noise tolerance. To reduce the leakage power, a sleep transistor is added to the dynamic node which turns off the high threshold voltage transistors. The total power consumption is reduced by 34.73% and the delay of the circuit is improved by 48.32% for the appropriate value of the W/L ratio. The simulation has been done on cadence virtuoso tool with 90nm technology with gpdk library at different voltages.
