ABSTRACT
Multiple antennas are used in both the transmitter and receiver ends of MIMO systems to increase spectrum efficiency. The implementation of two methods of decoding algorithms, the Viterbo-Boutros (VB) as well as Schnorr-Euchner (SE), is proposed in this method. The decoding algorithm is divided into a single FPGA device using a software/hardware co-design methodology. To maximize the decoding efficiency, three methods of parallelism are being adopted: using a concurrent channel matrix, using preprocessing and parallel decoding of imaginary or real selection, and concurrent execution of many phases in the closest lattice point search. With a Xilinx FPGA chip, the decoders for a 4x4 MIMO system with 16-QAM modulation have been prototyped. The VB and SE algorithms have hardware prototypes that relate to the support data rates of up to 84.4 and 38.2 Mb/s at a 22 dB SNR, which is faster than their respective implementations in a DSP.
