ABSTRACT
This chapter covers latest advances in data converter design and focuses on Nyquist-rate ADCs. It provides a comprehensive analysis for various noise sources of the SAR ADC. Based on the analysis, the chapter presents multiple low-power techniques to reducing noise at both the transistor and the architectural levels. Approaches to reduce the DAC switching power are also described. Then, the chapter talks about how to boost SAR ADC speed and presents an array of techniques aiming at the reduction of the comparator delay, the logic delay, the DAC delay, the comparator reset time, and the number of comparison cycles. After that, it also talks about how to correct sparkle codes in high-speed SAR ADCs. Finally, the chapter also focuses on timeinterleaved ADCs and channel mismatch calibration.
