ABSTRACT
The presented neuromorphic circuits comprise synaptic weights and neurons including batch normalization, activation function, and offset cancelation circuits. These neuromorphic circuits comprise an effective 3.5 bits weight storage based on binary memory cells while the analog multiplication and addition operation is based on a voltage divider principle. To experimentally proof the working principle, three fully connected layers (50x20, 20x10 and 10x4) have been designed. The connection between these layers is realized completely in the analog domain without ADCs and DACs in between. An inference state machine takes care of pipelining the layers for a proper operation during inference. The schematic and layout of the neuromorphic circuits comprised in these layers have been automatically generated with a in-house designed automation framework. This framework, called UnilibPlus, is a Python-based Cadence Virtuoso add-on. Simulation results of weight loading, transfer of input values, inference and read inference results via SPI interface show a correct operation of the designed ASIC with 12 nJ per inference and 5 μs latency.
