ABSTRACT
As the scaling improves, the growth rate of semiconductor industries for the development of low-power VLSI chip design increases. In this chapter we are using CNTFET-based interconnects for the implementation of existing and proposed designs to enhance the performance parameters such as power, delay, etc. The main concern in an interconnect device is propagation delay, because as wire length gate increases, the delay of the signal also increases. Here we present the designs for three proposed circuits with leakage mitigation technique using CNTFET interconnects. In order to compare all repeaters and buffers currently in use, multiple combinations of MOS repeater Cu interconnect and CNT repeater CNT connection were used. In addition to lowering average power usage, the proposed repeater incorporates power gating techniques and an automated toggling approach to reduce delay. The proposed design reduces dynamic power by 99.94% and leakage power by 93% when compared to conventional buffers, but there is a delay penalty when using typical RLC interconnects. The proposed design uses LECTOR RLC interconnects to reduce latency by 52% and save 99.86% of dynamic power and 88.6% of leakage power. While the proposed design reduces propagation delay by 64% and dynamic power usage by 98%, it does so at the expense of leaky power consumption when using Galeor RLC interconnects. By employing the Stanford SPICE model for CNT and the BSIM4 PTM model for MOS, simulation for 32 nm is carried out in HSPICE by treating a portion of a long interconnect line as the driver interconnect load system.
