ABSTRACT
In conventional memory cells such as SRAM cells, used in satellite and aerospace applications, exposure to high amounts of radiation causes single-event upsets (SEU). An SEU causes the voltage of a particular node to change temporarily after the impact of radiation, which can eventually lead to bit-flip or soft error. The conventional 6T SRAM cell cannot recover from SEU because as one of the storage nodes gets affected by SEU, it will drive the other node as well because of the cross-coupled inverter mechanism. Therefore, a need arises for a radiation-hardened SRAM cell. This chapter proposes a novel Proposed12T SRAM cell that has the capability to recover from SEUs induced at sensitive nodes as well as multiple-node upset recovery caused at the storage pair (S0-S1), which is achieved by isolating the charge-storing nodes (Q-QB) from internal nodes S0-S1 using two NMOS transistors in the pull-up path. The relative strength of Proposed12T cell over RHMD10T, RHM-12T, QUATRO-12T, and QUCCE-12T is determined by comparing the read delays, write delays, static noise margin (SNM), critical charge, hold power consumption, relative area, and SEU occurrence probability. The simulations are done using 65-nm technology. When compared to the RHMD-10T cell, the Proposed12T SRAM cell is able to provide self-recovery from the multiple-node upset at node pair S0-S1. The Proposed12T cell exhibits 1.083x/4.159x/3.909x improved critical charge compared to RHMD-10T/QUATRO-12T/QUCCE-12T and 1.105x/1.063x/1.079x higher write stability than RHMD-10T/QUATRO-12T/QUCCE-12T. Furthermore, the Proposed12T cell consumes the lowest hold power than any other comparison cell. However, these gains come at the expense of a moderate read static noise margin.
