ABSTRACT
Customers are increasingly demanding portable digital systems that offer comparable performance to nonportable systems but with smaller size and longer battery life. In response, inventors are turning to low-power very large scale of integrated circuit (VLSI) design, which reduces the supply voltage of the integrated circuit to diminish dynamic power dissipation in micrometer technology-based devices. This was a primary concern of total power dissipation.
To enhance circuit speed with the lower voltage, the threshold voltage (VTH) of the transistor is also reduced. However, as VTH is exponentially proportional to the sub-threshold leakage current (ISUB), it increases the sub-threshold leakage power, which is becoming more dominant in nanometer technology–based devices.
Furthermore, technology scaling increases the short channel effect as well as drain-induced barrier lowering (DIBL) effect. As a result, gate oxide tunneling current is also affecting device performance during static conditions.
This work focuses on input vector control (IVC) technology due to its independency on transistor technology. It is applicable on lower logic depth digital circuit. Therefore, a variant-based gate modification (VGM) algorithm is used for reduction in leakage power dissipation, and the proposed techniques are integrated with Fin-FET technology to reduce the short channel effect as well as DIBL effect.
The proposed approach is applied to logic gates and benchmark circuits on a HSPICE simulator to validate its behavior. This work uses different variants of a given conventional logic gate. As per the requirement, a particular variant is used to minimize the leakage. Maximum of 80.53% leakage power was reduced. This work is done with the technology of 32 nm at 25°C temperature. Behavior of the applied technique gives the similar reduction in leakage, hence the proposed technology is technology independent and environment independent.
