ABSTRACT
This chapter describes a method for computing the parasitic resistive and capacitive coupling in VLSI circuits. The method is based on the geometry of the coupling mechanism and the derived model is scalable and technology independent. The accuracy of the method is validated using simulation data from commercial simulators as well as measurements obtained from a test chip fabricated in the UMC 0.18-μm BiCMOS lightly doped process. A new approach for extracting the substrate resistance is also proposed in this chapter. It relies on the geometric interpretation and the prediction of the current streamlines between two-coupled structures. It is general, it requires a small number of simple-DC measurements and it does not use fitting techniques. Extensive simulation experiments on various substrates types have been performed. Also, measurements based on a fabricated chip have been used to validate the proposed method. All results show that the average error in resistance computation is within 5%, supporting the validity of the proposed method.
