ABSTRACT
As the market pushes for advanced applications, integrated circuits' (ICs) frequency increases up to the millimeter wave range, enabling faster computer cycles and data transmission. However, higher operating frequency increases the crosstalk through the silicon substrate between on-chip devices. In this chapter, interconnections and inductors are simulated leveraging ANSYS HFSS and presuming a typical 65 nm CMOS technology. The crosstalk between them and means to isolate them are studied, by extracting and comparing the s parameters of the simulated structures. The substrate proves to be deteriorating the inductors' quality and further increasing their crosstalk, especially at higher frequencies and greater separation distances. Guard rings and shields placed around and beneath the inductors respectively are also simulated in several topologies, increasing the isolation between them. Simulated structures are compared to each other regarding the quality of the inductors, the area they occupy, the crosstalk and the unwanted resonance points that might occur.
