ABSTRACT
Models of coupling noise from an aggressor module to a victim module by way of through substrate vias within heterogeneous 3D-integrated circuits are presented in this chapter. Existing TSV models are enhanced for different substrate materials within heterogeneous 3D-ICs. Each model is adapted to each substrate material according to the local noise coupling characteristics.
The models are numerically verified and evaluated in the time domain using SPICE. The effect of the inductance of the ground network on the peak noise at the victim circuit is determined for Si, Ge, and GaAs substrate materials. The effectiveness of certain noise mitigation techniques is evaluated. A maximum reduction in substrate noise of up to 77.9% and ~100% is exhibited with a shallow guard ring for, respectively, Si and Ge substrate materials.
