ABSTRACT
Planar scaling of integrated circuits (ICs) following Moore's law is approaching its limits. As an alternative, 3D technologies follow a more-than-Moore strategy, which has the potential to significantly boost the performance and capabilities of state-of-art ICs while supporting the integration of heterogeneous technologies. Among such 3D technologies, the through silicon via (TSV) process has become a key breakthrough to shorten global interconnects and enable the heterogeneous integration of different technologies. However, TSVs are also an important source of noise coupling in high-speed and high-frequency applications and can interfere with the operation of neighboring devices and circuits through the TSV oxide liner and the conductive silicon substrate. This can cause circuit malfunctioning and signal integrity problems.
