ABSTRACT
This chapter focuses on how substrate noise isolation can be improved in low-cost standard CMOS processes without any additional masks or modifications of the process flow. The isolation techniques and structures that are presented, described, implemented and tested are fully compatible with single well processes. To improve the isolation of the classical guard-ring structures in low cost CMOS technologies, it is necessary to create a pseudo deep n-well region or block the p-well implant in some regions, which can be achieved through careful masks manipulation. The experimental results clearly show that it is possible and feasible to implement high-noise isolation structures, usually only available in advanced and highly cost technologies, in low-cost standard CMOS processes. The proposed solutions achieve noise isolations as high as 65 dB from DC to 6 GHz.
