ABSTRACT
With the scaling down of MOS transistors in the nanoscale (sub-90 nm) regime, physical operation of a transistor becomes complex, which seriously affects the performance of the device. This chapter introduces the basic idea of scaling and the scaling rules. The major short-channel effects of the MOS transistors are subsequently introduced. These include threshold voltage roll-off, drain-induced barrier lowering, and dependence of the inversion carrier mobility on the lateral and horizontal electric fields. In the nanoscale regime, the transistors become leakier. The leakage currents are introduced in this chapter. It then presents in a comprehensive manner the various approaches to mitigate the detrimental effects of the short-channel effects. These are broadly classified into three categories: channel engineering, halo/pocket engineering, and novel device architectures. The ultrathin body device structure and the multigate structure are the two recent structures used for the MOS transistor. This chapter presents an introductory overview of these structures. Finally, it introduces the epitaxial delta-doped channel MOS transistor, which, being based on the planar bulk MOS technology, has recently gained a lot of interest among researchers. The objective of this chapter is, therefore, to present in a nutshell the short-channel effects and their solution approaches for nanoscale MOS transistors.
