ABSTRACT
The pursuit of reduced parasitic junction capacitance led to the development of silicon-on-insulator device technology in the 1990s. Planarization technology prior to interconnect metallization had been explored early in the semiconductor industry, relying on reflow of doped glass dielectric. A transition from dimensional scaling with a single level of complementary metal–oxide–semiconductor devices may come to an end. Examples of “cleverness’’ in device architecture and process technology are found in abundance throughout the history of the semiconductor industry. Taking a holistic approach to patterning process development in view of device process technology and circuit design has become a new frontier in enabling device scaling. Source mask optimization technology leverages pixelated illumination and co-optimized masks to improve design space coverage and patterning process window on wafer. Pulsed plasma technology has also been explored to enhance etch selectivity by achieving a finer degree of control of the ion energies and chemical species present in the plasma.
