ABSTRACT
The ecosystem has historically featured so-called integrated device manufacturers spanning both integrated circuit (IC) design and manufacturing functions, as well as semiconductor foundries that produce chips for fabless design companies. The unsung hero of the arduous challenge to keep IC performance on track has been and continues to be a heterogeneous set of computationally intensive computer-aided design methodologies collectively known as design technology co-optimization or design tor manufacturing. Fundamental to the economics of semiconductor manufacturing and its relationship to electronic design is the concept of metal–oxide–semiconductor field-effect transistor device scaling, sometimes referred to as Dennard scaling. The goal of the fab process, of course, is to manufacture a given integrated circuit chip with as high a yield as possible, and to do so immediately upon introduction into manufacturing. Dose can serve as a proxy for a variety of different manufacturing process excursions, such as postexposure bake time and temperature.
