ABSTRACT
In chip multiprocessor (CMP) architecture, the last level cache (LLC) is shared by multicore processors and has a significant influence on performance. Therefore, as the CMP architecture has become more widely used, LLC-related research has drawn increased attention. With an increase in chip capacity and area, the differences in cache bank access time in LLC increase significantly. If all cache banks use the same access latency, the performance can be limited by the cache banks that have the largest access latency. This chapter introduces the spin-transfer torque random-access memory (STT-RAM) background and the related work for the hybrid cache. It presents proposed 3D stacked hybrid cache with the access-aware technique and the dynamic partitioning algorithm. Some cache partitioning algorithms have been proposed to determine the cache partition size dynamically for each core to improve the cache utility. The nonuniform cache access (NUCA) architecture is used in the proposed 3D stacked hybrid cache architecture.
