ABSTRACT
This chapter focuses on the hardware design portion of the 60 GHz transceiver system on chip (SOC), which is controlled by Serial Peripheral Interface (SPI). The transceiver architecture, including the transmitter and the receiver is important for the targeted SOC performance. The selection of the architecture is determined mainly by the applications, bandwidth, power consumption as well as the integrated circuit (IC) process capability, etc. The 60 GHz transceiver SOC is better to cover all of the 60 GHz applications worldwide; thus, the 9 GHz bandwidth with four frequency channels is targeted to cover the frequency band of the USA, Europe, Japan, China, etc. The 60 GHz transceiver SOC has the re-configurable capabilities for both gain and operation frequency bands covering 9 GHz bandwidth in total. The SOC is designed and fabricated in Tower Jazz Semiconductor using 0.18 gm SiGe bipolar process SBCH2, where hetero-junction bipolar transistor (HBT) transistors have fT/fMAX of 180 GHz/200 GHz.
