ABSTRACT
This chapter presents an overview of various sources of variability in nanoscale devices and circuits. It discusses the device-level process variability mitigation using planar Metal Oxide Semiconductor (MOS) technology. The chapter presents the nominal substrate bias and mismatch characteristics for the device. It gives an overview of different sources of variability in nanoscale devices and circuits. The chapter shows that with a suitable choice of channel profile parameters, the device can give acceptable device variability mismatch characteristics with some compromise with the intrinsic gain. The primary reason behind the degradation of intrinsic gain of MOS transistors is the degradation of the output resistance, caused by the drain-induced barrier lowering effect. Hence, epitaxial delta doped channel MOS transistor, being based on bulk complementary MOS technology, is a promising approach for extending the scalability of bulk MOS technology for low power system-on-chip applications.
