ABSTRACT
This chapter discusses the effect of ground plane and strained silicon in different field-effect transistor (FET) device structures along with their implementations issues. It introduces the concept of ground plane in silicon on insulator (SOI) structures and the method of incorporation in fully depleted silicon on insulator and fin field-effect transistor (FinFET) devices. The chapter illustrates the concept of straining silicon and its advantages over conventional silicon devices It also describes different methods of introducing the strain in silicon. The chapter emphasis is given on the structure of strained SOI and strained FinFET devices. It discusses the concept of ground plane in SOI device structures, the use of which can reduce the off-state leakage current and optimize it for the low-power applications. Therefore, in nanoscale devices with a very short channel length, it is not possible to achieve both reduced drain-induced barrier lowering effect and steep subthreshold slope.
