ABSTRACT
This chapter describes new switch architectures such as input/output buffer types, input buffer and multi-stage switches. It details the Input/Output buffer type switch with feedback loop. Head-of-line blocking is reduced by employing a feedback loop from the blocked output buffer. The chapter proposes an input-buffered switch architecture based on a virtual-output-queued structure supporting Quality of Service. It offers both deterministic, i.e., firm, and stochastic delay bounds per connection for prioritized traffic. Asynchronous transfer mode (ATM)-Passive Double Star is a very cost-effective way to realize many ATM transfer capabilities. A pipelined-based maximal-sized matching scheduling approach is proposed. Each sub-scheduler is allowed to take more than one time to complete maximal-size matching. A packet concentrator is useful since it simplifies output-buffered switches. The proposed concentrator has a significantly smaller probability of packet loss. The final paper of this chapter studies a distributed traffic control scheme for large multistage ATM switching system.
