ABSTRACT
This chapter describes the 3D chip integration process development and the results of characterization of die-to-wafer 3D integration. It discusses the advantages of 3D integration technology. The chapter reviews the various kinds of 3D integration technology, including their advantages and limitations. It also discusses that the Cu/Ni/In chips, formed without intermetallic compounds (IMCs) throughout the pad's volume, had better resistance to impact shocks than the Cu/Sn samples with brittle IMC formed in their interfaces. For 3D system integration, the thinned chips are stacked directly onto other chips, and they are connected electrically by using vertical interconnections. One of the key technologies for 3D chip fabrication is how the vertical interconnections are formed, which includes Through-silicon via (TSV) and bonding technologies. The chapter focuses on deep thermal cycle (DTC) testing of the die stack systems with the Cu/Ni/In and Cu/Sn IMC bonding interconnections.
