ABSTRACT
This chapter presents the fabrication and modeling approach for Cu- and CNT-based through-silicon vias (TSVs). Designing and fabrication of novel devices is essential for providing more functionality at higher speed and in smaller dimensions. A 3D integrated circuit (IC) offers an alternative solution to 2D planar ICs by either increasing the device functionality or combining different technologies. TSVs are electrical interconnects that vertically penetrate through stacked wafers or chips. This methodology also effectively reduces the mechanical strain. The chapter provides the details of electrical and thermomechanical properties. It also provides a detailed description related to different steps of TSV fabrication. The chapter discusses the formulation of different parasitics that are associated with Cu-based TSV. It presents three different equivalent electrical models of single-walled carbon nanotube (SWCNT) bundle-based TSVs. The equivalent models primarily represent the schematic of a pair of SWCNT bundle TSVs. In the fabrication process, the diameter of SWCNTs can be controlled, which results in reduced ohmic resistance.
