ABSTRACT
Department of Information Technology, Bengal Engineering and Science University, Shibpur, India
Soumyajit Poddar
School of VLSI Technology, Bengal Engineering and Science University, Shibpur, India
10.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285 10.2 Evolution of Interconnects for Multicore Architectures . . . . . . . . . 286
10.2.1 More than Moore Trends: A New Perspective . . . . . . . . . . 287 10.2.2 From Single Bus Based to Network-on-Chip
Architectures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288 10.2.3 On Chip Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290
10.3 Emerging Technologies for Interconnections . . . . . . . . . . . . . . . . . . . . . 291 10.3.1 Three Dimensional Interconnects . . . . . . . . . . . . . . . . . . . . . . . 291 10.3.2 Photonic Interconnects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292 10.3.3 Wireless Interconnect Technology . . . . . . . . . . . . . . . . . . . . . . . 295 10.3.4 RF Waveguide Interconnects . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296 10.3.5 Carbon Nanotubes (CNT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296
10.4 Conclusion and Future Research Directions . . . . . . . . . . . . . . . . . . . . . 298
How do we exploit current technology to harness the full power of parallel computing architectures within the constraints of minimum energy, die-area, and complexity? Finding a viable answer to the above question needs a paradigm shift from the 1990s philosophy that a better processor has a functionally better and faster arithmetic logic unit (ALU) than its predecessor. Today’s process technologies are producing transistors in the Deep Sub-Micron (DSM) regime. These devices operate at GHz (gigahertz) frequencies at pico Watt power lev-
Architecture,
els. Using these devices, it is possible to integrate several different types of functionalities into the processor itself. Also, Moore’s Law has been followed quite well over the past few years. However, the current level of progress has reached a communication bottleneck in terms of interconnect and intra-chip communication resources. The latter problem is solved by putting emphasis on designing a reliable and efficient Network-on-Chip (NoC). Interconnects using metal wires have several issues for distributing both signals and clocks across the chip, e.g., power consumption of wires and use of repeaters. The remainder of this chapter discusses, from a communication viewpoint, the role of current and future interconnects used in multicore architectures.
