ABSTRACT
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Networks-on-chips (NoCs) provide a high performance, scalable and powerefficient communication infrastructure to both chip multiprocessor (CMP) and system on chip (SoC) systems [63]. A NoC usually consists of a packet-switched on-chip micro-network, foreseen as the natural evolution of traditional busbased solutions, such as Amba AXI [2], and Ibm’s Core Connect [35]. Innovative NoC architectures include the Lip6 SPIN [1], the M.I.T. Raw [79], the VTT (and various Universities) Eclipse [24] and Nostrum [25], Philips’ Æthereal NoC [27], and Stanford/Uni-Bologna’s Netchip [5, 36].
