ABSTRACT
Arindam Mukherjee, Arun Ravindran, Bharat Kumar Joshi, Kushal Datta and Yue Liu
Electrical and Computer Engineering Department University of North Carolina Charlotte, NC, USA {amukherj, aravindr, bsjoshi, kdatta, yliu42}@uncc.edu
10.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338
10.1.1 Why Is Autonomous Power Management Necessary? 339
10.1.1.1 Sporadic Processing Requirements . . . . . 339
10.1.1.2 Run-time Monitoring of System Parameters 340
10.1.1.3 Temperature Monitoring . . . . . . . . . . 340
10.1.1.4 Power/Ground Noise Monitoring . . . . . . 341
10.1.1.5 Real-Time Constraints . . . . . . . . . . . 341
10.2 Survey of Autonomous Power Management Techniques . . . . . 342
10.2.1 Clock Gating . . . . . . . . . . . . . . . . . . . . . . 342
10.2.2 Power Gating . . . . . . . . . . . . . . . . . . . . . . 343
10.2.3 Dynamic Voltage and Frequency Scaling . . . . . . . 343
10.2.4 Smart Caching . . . . . . . . . . . . . . . . . . . . . . 344
10.2.5 Scheduling . . . . . . . . . . . . . . . . . . . . . . . . 345
10.2.6 Commercial Power Management Tools . . . . . . . . . 346
10.3 Power Management and RTOS . . . . . . . . . . . . . . . . . . 347
10.4 Power-Smart RTOS and Processor Simulators . . . . . . . . . . 349
10.4.1 Chip Multi-Threading (CMT) Architecture Simulator 350
10.5 Autonomous Power Saving in Multi-Core Processors . . . . . . 351
10.5.1 Opportunities to Save Power . . . . . . . . . . . . . . 353
10.5.2 Strategies to Save Power . . . . . . . . . . . . . . . . 354
10.5.3 Case Study: Power Saving in Intel Centrino . . . . . 356
10.6 Power Saving Algorithms . . . . . . . . . . . . . . . . . . . . . 358
10.6.1 Local PMU Algorithm . . . . . . . . . . . . . . . . . 358
10.6.2 Global PMU Algorithm . . . . . . . . . . . . . . . . . 358
10.7 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 360
Review Questions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362
Bibliography . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363
Portable embedded systems place ever-increasing demands on highperformance, low-power microprocessor design. Recent years have witnessed a dramatic transition in the expectations from, and the capabilities of, embedded systems. This in turn, has triggered a paradigm shift in the embedded processor industry, forcing manufacturers of embedded processors to continually alter their existing roadmap to incorporate multiple cores on the same chip. From a modest beginning of dual and quad cores that are currently available in the 45 and 32 nm technologies, multi-core processors are expected to include hundreds of cores in a single chip in the near future. In SuperComputing 2008, Dell announced that it will release a workstation containing an 80-core processor around 2010 [1], and Intel is planning a 256-core processor in the near future. While the industry focus is on putting higher numbers of cores on a single chip, the key challenge is to optimally architect these processors for low power operations while satisfying area and often stringent real-time constraints, especially in embedded platforms. This trend, together with unpredictable interrupt profiles found in modern embedded systems, motivates the need for smart power saving features in modern embedded processors.
