ABSTRACT
As complementary metal oxide semiconductor (CMOS) technology continues to scale, power dissipation and robustness to leakage, noise, and process variations are becoming major obstacles for circuit design in these nanoscale regimes. This chapter discusses challenges and design solutions for high-performance energy-efficient register file circuit design. It reviews novel high-speed and leakage/process-tolerant register file circuits. The chapter describes the organization of the 4-read, 4-write ported 128 × 64b register file, the fully time-borrowable two-phase timing plan, and clock generation circuits. It reviews the bitline active leakage scaling issues of local bitline (LBL) and global bitline (GBL) schemes. In a dynamic LBL or GBL, at the time of evaluation, clock goes high, which turns off the precharge transistor. During this period, LBL and GBL are susceptible to noise due to high active leakage if the dynamic node is supposed to stay high. The chapter presents different leakage/process-tolerant circuit techniques.
