ABSTRACT
This chapter identifies major impairments to multi-Gbps chip-to-chip links, describes techniques to model them, and surveys the methods being used to mitigate those impairments and enable future links. It also describes equalization, including its implementation at the transmitter and the receiver. Forward equalization at the receiver may be performed by either a discrete-time filter or a continuous-time filter preceding the decision device. Unlike a de-emphasis filter, which processes digital inputs, a linear receive equalizer must be capable of handling the full dynamic range of signals that can appear at the receiver front-end, generally making it a more challenging circuit design. The chapter compares different modulation schemes. A common criterion for selecting an appropriate modulation scheme is examined and found to be oversimplified. In parallel bus chip-to-chip links dominated by self-crosstalk, deciding which modulation to use is complicated by the fact that both the signal and noise are influenced by the transmitted spectrum.
