ABSTRACT
Offering significant advantages in terms of low power, low voltage, and monolithic integration, complementary metal oxide semiconductor (CMOS) technology allows for the fabrication of so called "smart" image sensors. This chapter considers power reduction in state-of-the-art smart CMOS image sensors. It aims to present where power is dissipated in CMOS imagers and to figure out possible solutions to reduce this power dissipation. The chapter also presents sources of power dissipation in CMOS image sensors with reference to smart image sensor architectures. Then, considerations for power reduction in state-of-the-art smart CMOS image sensors are discussed, showing practical examples, where the mentioned techniques can be useful. The chapter shows that power dissipation can be reduced at all design levels–technology, device, circuit, logic, architecture, algorithm, and system integration. The interaction between the different design levels and their influence on general power dissipation is also presented.
