ABSTRACT
Many video processing applications employ spatial image transforms such as block-matrix and convolutional transforms. This chapter presents a mixed-signal very large-scale integration (VLSI) implementation of a digital complementary metal oxide semiconductor (CMOS) imager computing block-matrix and convolutional transforms on the focal plane for real-time image processing. The computational image sensor combines image acquisition, signal processing, and quantization in a single compact low-power architecture. The approach combines weighted spatial averaging and oversampling quantization in a single algorithmic sigma–delta-modulated analog-to-digital converter (ADC) cycle, making focal-plane computing an intrinsic part of the quantization process. The approach yields power dissipation below that of a conventional digital imager while the need for a peripheral digital signal processor (DSP) is eliminated. The chapter compares the presented architecture with a conventional approach where column-parallel algorithmic ADCs performing no computation are employed and an additional peripheral serial digital multiplier and accumulator performs video compression.
