It has been noted by the digital design community that the greatest potential for additional cost and iteration cycle time savings is through improvements in tools and techniques that support the early stages of the design process. What is needed is a design environment in which the capability for performance modeling of HW/SW systems at a high level of abstraction is fully integrated into the engineering design environment. This environment must support the incremental refinement of the abstract system-level performance model into an implementation-level model. In addition to the problem of mixed-level modeling interfaces, another issue that may have to be solved is that of different modeling languages. While VHDL, and to some extent various extensions to Verilog, can be used to model at the system level, many designers constructing these types of models prefer to use a language with a more programming language-like syntax. As a result of this and other factors, the SystemC language was developed.