ABSTRACT
Many products require efficient high-performance processing to meet the growing computational requirements of numerous media applications. Tailoring a processor’s architecture and system interfaces to minimize processing overhead and inefficiencies in data transfers is required to provide efficient processing for these media applications. In addition, efficiency and low power require the use of techniques that remove the dependency on the
CONTENTS
4.1 Introduction ................................................................................................. 107 4.2 The RACE-H Architecture ..................................................................... 109 4.3 The RACE-H Processor Platform .......................................................... 116 4.4 Video Encoding Hardware Assists .......................................................... 119 4.5 Performance Evaluation ............................................................................. 120 4.6 Conclusions and Future Extensions ........................................................ 122 Trademark Information ...................................................................................... 122 References ............................................................................................................ 122
processor clock speed to obtain adequate performance. Applications such as high-definition (HD) multistandard video processing require almost continuous processing at the highest performance level. Because power use is highly dependent on frequency, very little power savings can be achieved in these high-compute applications by varying clock frequencies to minimize power use during less-demanding program segments. Use of a flexible parallel architecture is an important means to provide high performance without having a high dependence on the clock rate.
