ABSTRACT
The goal of the test process for integrated circuits is to separate good devices from bad devices, and to test good devices as good. Bad devices tested as bad become yield loss, but they also represent opportunity for cost reduction as we reduce number of defects in the process. Unfortunately, the test environment is not the same as the operating environment. The test process may reject good devices and may accept defective devices as good. Bad devices are removed from good devices through a series of test techniques that enable the separation, by either voltage- or current-based testing. The most widely used fault model is the single stuck-at fault model. It is available in a variety of simulation environments with good support tools. The model represents a defect as a short of a signal line to a power supply line. Parametrics tests ensure the correct operation of the transistors of the integrated circuit.
