ABSTRACT

This chapter describes architectural techniques appropriate for reducing power and energy in caches. It also describes conventional cache design, and considers the sources of energy dissipation and degrees of freedom in the low-power design space. The chapter presents an in-depth survey and in many cases analyses of cache energy reduction techniques. There are two major components of energy dissipation in cache: dynamic energy, which is attributed to signal transitions in activated bit- and word-lines, sense-amplifiers, comparators, and selectors during reads/writes, and static energy, which is due to the total amount of leakage current, through inactive or OFF-transistors. High access rate directly increases the number of tag checks and data reads, magnifying the cache energy consumption proportionally. The main disadvantage of the block buffering is cache-access latency increase. The chapter discusses several degrees of freedom are inherent in cache organization: cache size, associativity, block size, and tag size.