ABSTRACT

This chapter provides an overview of digital testing techniques, with reference to material containing details of methodologies and algorithms. Pseudorandom pattern generation is the main alternative when Built-in self-test is introduced, because the overhead costs of storing even a minimal test set would be impractical in circuit testing. Accessibility to internal dense circuitry is becoming a greater problem. It is essential that a designer consider how a device will be tested and incorporate structures into the design to help that testing. The primary objective of testing digital circuits at chip, board, or system level is to detect the presence of hardware failures induced by faults in the manufacturing processes or by operating stress or wearout mechanisms. Pseudo-random testing achieves many of the benefits of exhaustive testing but requires much fewer test patterns. Path-delay testing is aimed at testing whether a given component/system operates at a specified performance level that is often measured as the maximum system clock frequency.