ABSTRACT
The clock speed increases, the number of logic levels in the critical path diminishes. The ability to absorb clock skew and to use a faster clocked storage element (CSE) results in direct and significant performance improvements. The two most important timing parameters affecting the clock signal are: clock skew and clock jitter. The clock skew is a spatial variation of the clock signal as distributed through the system. Clock jitter is a temporal variation of the clock signal with regard to the reference transition of the clock signal. The traditional view of the finite state machine is represented by the Huffman model, which consists of combinational logic and CSEs. The function of a CSE is to block the signal path, thus preventing it from corrupting the present state. The clocking for high–performance and low–power systems represents a challenge given the rapid increase in clock frequency, which has already reached multiple GHz rates.
