ABSTRACT
The design automation tools for analysis and optimization are key enablers for low-power design. The power analysis tools need to provide a detailed, time–based power analysis capability for full chips. The clock gating involves dynamically shutting off the clock to portions of a design that are idle or are not performing useful computation. The granularity of the circuit block at which clock gating is applied greatly affects the power savings that can be achieved because gating larger blocks results in higher power savings in the “off” clock cycle, but allows fewer number of “off” clock cycles. The difference in the latencies is the delay of the clock–gating circuit and the clock tree between the clock gate and the registers. The impact on the clock–tree is minimal because the clock–gating cells are placed close to the registers and can eliminate the need for post clock–gating cell buffer insertion.
