ABSTRACT
This chapter discusses the design and application of systolic arrays. It presents the development of a beamformer to demonstrate an intuitive design process of an application-specific processor. The chapter introduces a number of high performance processor design examples, including a real-time fast Fourier transform, a high performance QR decomposition for adaptive beamforming, and a very-large-scale integration bit-level systolic array finite impulse response filter. A systematic approach for the design and analysis of systolic arrays is explained, and a number of high performance processor design examples are provided. A systolic array consists of an arrangement of processing elements (PEs), optimally designed and interconnected to explore parallel processing and pipelining in the desired signal processing task. A straightforward implementation of a beamformer is, therefore, to provide four beamformer modules to form four concurrent beams in parallel. Since the sensor outputs are used in different pipeline stages, apparently buffers are needed to hold the samples until they are used in the pipelined computation.
