ABSTRACT
This chapter focuses on the architecture, design, and implementation approaches of a representative space–time adaptive processor. This application is particularly interesting in the context of a high performance embedded computing (HPEC) system perspective. It exemplifies a hybrid implementation between dedicated hardware for very regular processing functions in the front–end of the prototype system and programmable hardware for back–end processing demanding less computation. The system application illustrates here is an airborne early warning prototype for detecting targets buried in jamming and clutter interference. A way to describe the important signal processing functions necessary to ultimately achieve the goal of detecting a target is to separate these functions into three successive categories: digital filtering, adaptive signal processing, and post–adaptive signal and data processing. The data are first processed through the stages of baseband quadrature sampling to focus the data to the bandwidth of interest. The development of a complex HPEC system involves careful attention to the overall system design.
