ABSTRACT
Critical charge to represent a logic state in Integrated Circuits (ICs) is steadily decreasing with the shrinking device technology feature sizes. Single-Event Effects (SEEs) induced by heavyion irradiation has become a primary reliability issue for deep submicron processes because of the reduced nodal charge and space between devices (P.E. Dodd, 2010 & D. Munteanu, 2008). Traditionally, the close proximity of transistors means that the deposited charge cloud from an ion strike is expected to encompass multiple transistors on ICs, resulting in multiple-node charge collection (termed charge sharing) in devices (O.A. Amusan, 2006). Thus, it is imperative to characterize the single-event transient response to different design and layout practices. Dual-well bulk CMOS technology has been the subject of extensive studies on improving the reliability of manufacturing space and military electronic devices. The effects of dual-well structure were mainly analyzed and results showed that Single-Event Transients (SETs) using the dual-well technology were shorter than those in the triple-well technology (T. Roy, 2008). Perturbations in n-well and p-well potentials also have been shown to affect strongly the
which are affected by dual-well structure. First, the schematic cross view of dual-well CMOS technology is illustrated in Figure 1. A particle strikes a sensitive region of a circuit module and deposits a dense track of electron-hole pairs, where the deposited charges will cause a potential gradient in the bulk from the strike location to the substrate, which could possibly activate the parasitic bipolar transistor of MOSFETs in the P-well and N-well, as well as affects the potential modulation process of multiple junctions.
