Simulation of Single-Event Effects on Fully Depleted Silicon- on-Insulator (FDSOI) CMOS

These devices were used to design six-transistor static random access memory (6T SRAM) cells. These memories were simulated to observe single-event upset (SEU) faults due to heavy-ion impacts in different angles and locations. The 6T SRAM cells designed with FDSOI technology were more resilient against the heavy-ion impacts than the bulk ones.