ABSTRACT Stacked integrated circuits with copper-filled through silicon vias (TSVs) are a common component of three-dimensional integration concepts in microelectronics. The interfaces of the resulting Cu/Si composite material are affected by diffusional interfacial sliding which leads to TSV intrusion or protrusion. The resulting differential strain of the Cu TSV and the Si matrix affects the performance of the transistor or the reliability of interconnects close to the TSV. This may limit the use of stacked integrated circuits under harsh environment conditions.