ABSTRACT
Power and efficiency are a major concern in any digital system, and their minimization is tough in full-adder circuits. In the previous work on this topic, the energy consumption was in the range of microwatt. This paper proposes an efficient 14-transistor 1-bit full-adder circuit under a multithreshold voltage scheme. This circuit is designed using a Complementary Metal Oxide Semiconductor (CMOS) in 180-nm technology. The power consumption of this circuit is achieved in nanowatt scale for different frequencies; this is less than other existing adder circuits for the same testing condition. The design and implementation of the proposed model were analyzed and verified through the SPICE simulation platform and the average power consumed by this circuit was 17 × 10−9 W at an operating frequency of 500 MHz, which is less than the values for other conventional methods.
