ABSTRACT
In this paper, we implemented a Phase Locked Loop (PLL) to operate in higher frequencies and low power for wireless receivers. The PLL is implemented with proposed designs at block level. A new design is proposed for CP to avoid the current mismatch, which cause to produce spurs in the output of the PLL. A hybrid type of FD is proposed to enrich the power efficiency of the PLL. The efficiency is achieved at each block of the PLL. Therefore, Power Efficient PLL (PEPLL) for wireless communication is constructed and implemented by Tanner EDA tool. The parameters such as power and delay of the PEPLL are calculated using H-Spice for 180 nm technology at 2.0 V. The PEPLL consumes only 1.2155 mW of power and requires only 88 MOS devices.
