ABSTRACT
This chapter discusses the structural characterization by means of transmission electron microscopy for some advanced silicide processes. It investigates both blanket layers and narrow line structures. The chapter examines the influence of the initial layer stack on the epitaxial growth modes in the layer. Silicides are commonly applied in metal-oxide-semiconductor devices to lower the resistance between the metal contacts and the diffused source and drain areas, and as conductor on top of the poly-silicon gates. Epitaxial growth with the cube axes of the silicide and silicon aligned to each other results on silicon in unacceptably large overall interface roughness of the silicide layers. The development of the silicide preparation methods requires the analysis by electrical methods as well as physical techniques, among which transmission electron microscopy takes an outstanding role. The formation of the disilicide phase at low temperatures is reported before for very thin metal layer and after low temperature rapid thermal annealed.
