ABSTRACT
Network-on-Chip (NoC) architecture provides a communications infrastructure for the cores of a multi-core System-on-Chip (SoC). The NoC resources are connected to the SoC cores enabling them to communicate among each other concurrently by sending messages asynchronously. Complex router architectures are efficient for certain NoC configurations or data flow circumstances. Moreover, static vertical cavity (VC) buffers are the expensive components of NoC routers and they become more expensive for larger flit size or when the VC buffer depth becomes larger. The two above drawbacks of static VCs necessitate an adaptive VC organization to achieve VC flow control with maximum buffer utilization. The router arbiter can perform arbitration through four pipelined stages: Routing Computation (RC), Virtual- channel Allocation, Switch Allocation, and Switch Traversal. The structure of RC can be a simple multiplexer, due to XY routing considered for communication in a 2D mesh NoC. The router employs VC organizations, which is an amended version of Rapid Dynamic Queue employed in input-port modules.
